1. Field of the Invention
The present invention relates generally to digital displays and, more particularly, to interfaces that adapt analog display signals to digital displays.
2. Description of the Related Art
The cathode ray tube (CRT) has been the standard computer-display monitor for many years. Because CRTs have generally responded to analog display signals, there currently exists an extremely large installed base of computers (more than a billion) that incorporate digital-to-analog converters (DACs) configured to generate CRT analog display signals.
Recently, digital display devices (e.g., flat-panel displays, liquid crystal displays, projectors, digital television displays and near-to-eye displays) have become increasingly popular. Although it is anticipated that all-digital interfaces will eventually become the standard interface for these displays, analog interfaces must be available for the near future because of the large existing installation base of computers.
In response to the need for both analog and digital interfaces, an open industry group known as the Digital-Display Working Group (DDWG) has developed a digital-visual interface (DVI) specification which establishes analog and digital interface standards. In particular, these standards reference the Video Electronics Standards Association (VESA) specifications for the implementation of analog interfaces.
Analog-to-digital converters (ADCs) are typically used to adapt the analog display signals to a flat-panel display. The ADCs generally include high-speed samplers that provide analog samples which the ADCs then quantize into the desired digital display signals.
In order to assure accurate analog samples, the sample clock that actuates the samplers must be extremely stable (i.e., have low jitter) and be driven with extremely accurate clock signals. For example, a 640×480 pixel display with a typical refresh rate has a pixel processing period on the order of 40 nanoseconds but a large 1280×1024 pixel display reduces the pixel processing period to 8–9 nanoseconds. Because rise and fall times and ringing further reduce the time that each pixel's analog state is valid, it is not surprising that control of ADC samplers has been a persistent problem in analog interface structures.